1. Field of the Invention
The invention generally relates to damascene interconnect processes, and, more particularly, to a technique for monitoring the formation of voids in damascene structures.
2. Description of the Related Art
High density integrated circuits are typically formed with a multi-level interconnect structure having two or more layers of metal interconnects. The lowest level of interconnect wires is typically in contact with active regions of a semiconductor substrate but can also be in contact with, for instance, a conductor that leads to other devices that form part of a larger multi-chip structure. The different levels of interconnect wires are connected by metal plugs formed in openings in layers of insulating material that separate the levels of interconnect wires.
An important capability in the present art of semiconductor manufacturing is the damascene technology. That interconnect fabrication technology forms an interconnect structure by (i) etching a trench or via into a dielectric material, (ii) depositing the interconnect metallization to fill the trench or via, and then (iii) polishing the metal back to remove any metal from the surface of the substrate. An improvement over this so-called single damascene process is the dual-damascene process in which a second level is involved where a series of holes, i.e., contact holes or vias, are etched and filled, in addition to the trench. Thus, the dual-damascene process permits filling of both the conductive grooves or trenches, and the underlying vias at the same time.
A multi-level metal damascene interconnect structure is shown in FIG. 1. In this structure, a bottom metal trench 110 is formed in a substrate 100 and filled with a metal. On top of the substrate, a first insulating (dielectric) layer 130 is deposited. On top of the insulating layer 130 there is a second insulating layer 150 that has a top metal trench 140. The top metal trench 140 and the bottom metal trench 110 are interconnected by means of a via 120 which is a contact hole in the first insulating layer 130. The via 120 and the top metal trench 140 are filled with a metal.
As structures comprising integrated microelectronic circuitry continue to decrease in size, the conducting interconnects decrease in size as well. Smaller conducting interconnects must be composed of materials with lower resistivity. For this reason, copper has in recent times found more application in the use of metal wires because it offers significant advantages due to its low resistivity. The conductivity of copper is twice the conductivity of aluminum and three times the conductivity of tungsten, and copper thin films offer even lower resistivity than gold films. Copper has, therefore, been applied to damascene and dual-damascene schemes.
In copper damascene backend technologies, copper is normally deposited by using electroplating techniques. Electroplating of metals is a process that is widely used in the printed circuit board and multi-chip module technologies. In integrated circuit chip manufacture, in particular in ULSI (Ultra Large Scale Integration) processes, plating of metals, especially of copper, becomes a very attractive process. Electroplating processes utilize solutions containing ions of the metal to be deposited. In the case of copper, the solutions contain copper sulfate (CuSO4), sulfuric acid (H2SO4), and water. In electroplating, a relatively thin copper seed layer is deposited on the surface on which it is desired to deposit copper by using an electroplating process. The copper seed layer is immersed in this solution and it is electrically connected to become the cathode. As the positive cupric ions Cu2+ arrive at the cathode, they acquire two electrons and are reduced to copper metal, which plates out on the wafer surface. This process is continued until sufficient copper is formed on the wafer surface.
Generally, electroplating processes have high deposition rates and form desirable metallurgy. As mentioned above, copper electroplating requires a thin seed layer of copper that is about 50 nm thick and must first be deposited by some other method, such as chemical vapor deposition (CVD) or physical vapor deposition (PVD), onto an adhesion layer (also called barrier layer). Currently, two materials are used to form the barrier and seed layers. A barrier layer, such as titanium nitride (TiN) or tantalum/titanium nitride (Ta/TaN) or TaSixNy, is first deposited, with a copper (Cu) seed layer applied in a second step. To ensure that low-resistance vias are fabricated with high yield, the via pre-clean, barrier-layer deposition and seed-layer deposition steps are usually performed on a single vacuum-integrated sputter tool. The barrier layer and the seed layer together form the so-called base layer.
Turning now to FIG. 2, the electroplating process is depicted in more detail. The base layer deposition is usually preceded by a degas step 210 and a pre-clean sputter etching step 220. Then, the base layer is deposited by first depositing the barrier layer in step 230 and then depositing the seed layer in step 240. The actual copper electroplating process can then be performed in step 250.
The amount of energy introduced during the steps 210 and 220 of degassing and performing a via pre-clean can be relatively high and may heat up the wafer surface to temperatures above 300° C. Depositing the barrier layer and seed layer in steps 230 and 240 will then take place onto the hot wafer surfaces and causes high mechanical stress at the interface between the barrier layer and the copper of the metal line below. This stress can lead to voiding at the interface of the barrier layer to the copper.
Referring back to FIG. 1, the multi-level copper damascene interconnect structure shown in the figure includes the barrier layer 160 formed in step 230, and the seed layer 170 formed in step 240. The barrier layer 160 consisting of, e.g., tantalum (Ta) or tantalum nitride (TaN) has been deposited in step 230 onto the hot surface of the bottom copper trench 110. Thus, in the example of FIG. 1, interface voids could occur at the interface between the barrier layer 160 and the bottom metal trench 110.
Voids at the interface pose a serious reliability risk for the product since they influence the contact properties between the copper in the via 120 and the top metal trench 140, and the copper of the bottom metal trench 110. Due to voids, the contacts can become totally useless, but a more severe problem is that the contact behavior may change with time and may further depend on, e.g., the temperature at which the circuit is operated. Thus, the integrated circuit will no longer reliably work.
For this reason, interface voids have to be monitored. However, monitoring the formation of interface voids requires the steps of locating several damascene structures on the wafer, cross-sectioning the structures, and then observing the interface voids. To reliably monitor the occurrence and density of interface voids, it is therefore necessary to investigate a number of different structures since, on one and the same chip, some structures may have no voids while other structures do have voids. Due to the great effort involved in generating the samples for cross-section analysis, the inline interface void monitoring process is a very time-consuming process that slows down the integrated circuit development and manufacturing and further increases the production costs.
The present invention is directed to a method that may solve, or at least reduce, some or all of the aforementioned problems.